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fast page mode 4194304-bit (524288-word by 8-bit) dynamic ram m5m44800cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44800cj,tp-5,-5s:under development this is a family of 524288-word by 8-bit dynamic rams, fabricated with the high performance cmos process, and is ideal for large- capacity memory systems where high speed, low power dissipation, and low costs are essential. the use of double-layer metalization process technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. multiplexed address inputs permit both a reduction in pins and an increase in system densities. self or extended refresh current is low enough for battery back-up application. 1 description application microcomputer memory, refresh memory for crt features xx=j,tp type name access time (max.ns) ras access time (max.ns) cas (max.ns) access time address time (min.ns) cycle dissipa- (typ.mw) power tion m5m44800cxx-7,-7s m5m44800cxx-6,-6s 60 70 15 20 30 35 110 130 375 325 15 20 access time (max.ns) oe m5m44800cxx-5,-5s 50 13 25 90 450 13 pin description pin name a 0 ~a 9 dq 1 ~dq 8 ras w vcc vss cas function address inputs data inputs/outputs row address strobe input column address strobe input write control input power supply (+5v) ground (0v) output enable input oe fast page mode 4194304-bit (524288-word by 8-bit) dynamic ram m5m44800cj,tp-5,-6,-7, -5s,-6s,-7s mitsubishi lsis pin configuration (top view) standard 28pin soj, 28pin tsop (ii) single 5v?0% supply low stand-by power dissipation cmos lnput level 5.5mw (max) cmos input level 550? (max) * operating power dissipation m5m44800cxx-5,-5s 495mw (max) m5m44800cxx-6,-6s 413mw (max) m5m44800cxx-7,-7s 358mw (max) self refresh capability * self refresh current 150?(max) extended refresh capability extended refresh current 150?(max) fast page mode(1024-column random access),read-modify-write, ras-only refresh, cas before ras refresh, hidden refresh capabilities. early-write mode, cas and oe to control output buffer impedance 1024 refresh cycles every 16.4ms (a 0 ~a 9 ) 1024 refresh cycles every 128ms (a 0 ~a 9 ) * * :applicable to self refresh version (m5m44800cj,tp-5s,-6s,-7s :option) only 18 17 1 2 3 4 5 6 (5v)v cc dq 1 dq 2 a 0 a 1 a 2 v ss (0v) w ras cas oe a 3 a 4 a 7 a 6 a 5 a 8 21 28 dq 8 27 dq 7 26 25 19 20 outline 28p0k(400mil soj) 24 23 12 11 10 9 a 9 8 13 16 22 7 13 (5v)v cc 14 15 dq 3 dq 4 nc v ss (0v) dq 6 dq 5 nc 18 17 1 2 3 4 5 6 (5v)v cc dq 1 dq 2 a 0 a 1 a 2 v ss (0v) w ras cas oe a 3 a 4 a 7 a 6 a 5 a 8 21 28 dq 8 27 dq 7 26 25 19 20 outline 28p3y-h(400mil tsop normal bend) 24 23 12 11 10 9 a 9 8 13 16 22 7 13 (5v)v cc 14 15 dq 3 dq 4 nc v ss (0v) dq 6 dq 5 nc nc:no connection
fast page mode 4194304-bit (524288-word by 8-bit) dynamic ram m5m44800cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44800cj,tp-5,-5s:under development 2 function in addition to normal read, write, and read-modify-write operations the m5m44800cj, tp provides a number of other functions, e.g., fast page mode, ras-only refresh, and delayed-write. the input conditions for each are shown in table 1. operation ras cas oe inputs input/output refresh remark w row address address column input output read write (early write) write (delayed write) read-modify-write ras only refresh stand-by hidden refresh act act act act act act act nac act act act act nac act act dnc nac act act act dnc dnc dnc act dnc dnc act dnc act dnc dnc apd apd apd apd apd dnc dnc dnc apd apd apd apd dnc dnc dnc dnc opn vld vld vld dnc opn dnc dnc vld opn ivd vld opn vld opn opn yes yes yes yes yes yes yes no fast page mode identical note : act : active, nac : nonactive, dnc : don' t care, vld : valid, ivd : invalid, apd : applied, opn : open cas before ras (extended *) refresh self refresh * act act dnc dnc dnc dnc opn yes dnc dnc block diagram a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 address inputs clock generator circuit column decoder sense refresh amplifier & i /o control row decoder row & column address buffer memory cell (4194304bits) (8) data in buffer oe dq 1 dq 2 dq 3 dq 4 data inputs / outputs output enable input column address strobe input row address strobe input write control input cas ras w a 0 ~a 8 a 0 ~ a 9 v ss (0v) v cc (5v) v cc (5v) v ss (0v) dq 5 dq 6 dq 7 dq 8 table 1 input conditions for each mode (8) data out buffer
fast page mode 4194304-bit (524288-word by 8-bit) dynamic ram m5m44800cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44800cj,tp-5,-5s:under development 3 absolute maximum ratings symbol v cc v i v o i o p d t opr t stg parameter conditions ratings unit v v v ma mw -1~7 -1~7 -1~7 50 1000 0~70 -65~150 with respect to v ss ta=25?c supply voltage input voltage output voltage output current power dissipation operating temperature storage temperature recommended operating conditions (ta=0~70?c, unless otherwise noted) (note 1) unit limits min nom max v v v v 5.5 0 0.8 5.0 0 4.5 0 2.4 parameter supply voltage supply voltage high-level input voltage, all inputs low-level input voltage, all inputs v cc symbol v ss v ih v il 6.0 note 1 : all voltage values are with respect to vss. * * : v il(min) is -2.0v when pulse width is less than 25ns. (pulse width is with respect to v ss .) -0.5 * * electrical characteristics (ta=0~70?c, v cc =5v?0%, v ss =0v, unless otherwise noted) (note 2) note 2: current flowing into an ic is positive, out is negative. note 3: i cc1 (av) , i cc3 (av) , i cc4 (av) and i cc6 (av) are dependent on cycle rate. maximum current is measured at the fastest cycle rate. note 4: i cc1 (av) and i cc4 (av) are dependent on output loading. specified values are obtained with the output open. note 5: column address can be changed once or less while ras=v il and cas=v ih symbol v oh v ol i oz i i i cc1 (av) i cc2 i cc3 (av) i cc4(av) i cc6(av) high-level output voltage parameter limits min max unit typ test conditions low-level output voltage off-state output current input current average supply current from v cc, operating (note 3,4,5) (note 3,5) (note 3,4,5) (note 3,5) supply current from v cc , stand-by average supply current from v cc, ras only refresh mode average supply current from v cc, fast page mode average supply current from v cc , cas before ras refresh mode m5m44800c-5,-5s m5m44800c-6,-6s m5m44800c-7,-7s i oh =-5ma i ol =4.2ma q floating, 0v v out 5.5v 0v v in +6.0v, other inputs pins=0v ras, cas cycling t rc =t wc =min. output open ras= cas =v ih , output open ras cycling, cas= v ih t rc =min. output open ras=v il , cas cycling t pc =min. output open cas before ras refresh cycling t rc =min. output open v v ma ma ma ma ma vcc 0.4 10 10 90 75 2 0.1 * 90 75 65 2.4 0 -10 -10 ras= cas 3 v cc -0.5v output open 65 (note 6) m5m44800c-5,-5s m5m44800c-6,-6s m5m44800c-7,-7s m5m44800c-5,-5s m5m44800c-6,-6s m5m44800c-7,-7s m5m44800c-5,-5s m5m44800c-6,-6s m5m44800c-7,-7s 90 75 65 150 average supply current from v cc, extended-refresh mode (note 6) i cc8(av) * ras cycling cas 0.2v or cas before ras refresh cycling ras 0.2v or 3 v cc -0.2v cas 0.2v or 3 v cc -0.2v w 0.2v or 3 v cc -0.2v oe 0.2v or 3 v cc -0.2v a 0 ~a 9 0.2v or 3 v cc -0.2v, dq=open t rc =125?, t ras =t ras min~1? 1.0 80 65 55 150 average supply current from v cc, self-refresh mode (note 6) i cc9(av) * ras=cas 0.2v output open ?c ?c ? ? ? ?
fast page mode 4194304-bit (524288-word by 8-bit) dynamic ram m5m44800cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44800cj,tp-5,-5s:under development 4 switching characteristics (ta=0~70?c, v cc = 5v?0%, v ss =0v, unless otherwise noted, see notes 6,13,14) parameter access time from cas access time from ras column address access time symbol ns ns ns ns ns 15 30 35 60 13 25 30 50 access time from cas precharge (note 7,8) (note 7,9) (note 7,10) (note 7,11) (note 7) access time from oe 15 13 limits unit min max m5m44800c-5,-5s m5m44800c-6,-6s min max m5m44800c-7,-7s 20 35 40 70 20 min max t cac t rac t aa t cpa t oea 5 5 ns output low impedance time from cas low (note 7) 5 t clz output disable time after cas high output disable time after oe high 13 13 15 15 ns ns (note 12) (note 12) 20 20 t off t oez note 6:an initial pause of 500? is required after power-up followed by a minimum of eight initialization cycles (ras-only refresh or cas before ras refresh cycles). note the ras may be cycled during the initial pause. and 8 initialization cycles are required after prolonged periods (greater than 16.4ms) of ras inactivity before proper device operation is achieved. note 7:measured with a load circuit equivalent to 2ttl loads and 100pf. note 8:assumes that t rcd 3 t rcd(max) and t asc 3 t asc(max) . note 9:assumes that t rcd t rcd(max ) and t rad t rad(max) . if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac will increase by amount that t rcd exceeds the value shown. nor 10:assumes that t rad 3 t rad(max) and t asc t asc(max) . note 11:assumes that t cp t cp(max) and t asc 3 t asc(max) . note 12: t off(max) , t oez(max) defines the time at which the output achieves the high impedance state (i out ?0? ) and is not reference to v oh(min) or v ol(max) . capacitance limits min max unit typ pf pf pf input capacitance, address inputs c i (a) c i (clk) c i / o symbol parameter test conditions input capacitance, clock inputs input/output capacitance, data ports 5 7 7 v i =v ss f=1mhz v i =25mvrms (ta=0~70?c, v cc =5v?0%, v ss =0v, unless otherwise noted)
fast page mode 4194304-bit (524288-word by 8-bit) dynamic ram m5m44800cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44800cj,tp-5,-5s:under development timing requirements (for read, write, read-modify-write, refresh, and fast-page mode cycles) (ta=0~70?c, v cc = 5v?0%, v ss =0v, unless otherwise noted, see notes 6,13,14) note 13: the timing requirements are assumed t t =5ns. note 14: v ih(min) and v il(max) are reference levels for measuring timing of input signals. note 15: t rcd(max) is specified as a reference point only. if t rcd is less than t rcd(max ), access time is t rac . if t rcd is greater than t rcd(max) , access time is controlled exclusively by t cac or t aa . note 16: t rad(max) is specified as a reference point only. if t rad 3 t rad(max) and t asc t asc(max) , access time is controlled exclusively by t aa . note 17: t asc(max) is specified as a reference point only. if t rcd 3 t rcd(max) and t asc 3 t asc(max) , access time is controlled exclusively by t cac . note 18: either t dzc or t dzo must be satisfied. note 19: either t cdd or t odd must be satisfied. note 20: t t is measured between v ih(min) and v il(max) . 5 refresh cycle time (note 20) (note 15) (note 16) (note 17) 45 30 0 40 10 50 20 5 10 15 10 15 0 0 1 16.4 37 25 0 30 7 50 18 5 10 13 8 13 0 0 1 row address hold time after ras low transition time (note 18) (note 19) delay time, cas high to data ras high pulse width delay time, cas high to ras low cas high pulse width column address delay time from ras low row address setup time before ras low column address setup time before cas low delay time, oe high to data 0 0 0 0 15 13 15 13 (note 19) ms ns ns ns ns ns ns ns ns ns 50 35 0 50 10 50 20 5 10 15 10 15 0 0 1 0 0 20 20 ns ns ns ns ns ns t ref t rp t rcd t crp t rpc t cpn t rad t asr t asc t rah t cah t dzc t dzo t cdd t odd t t parameter symbol limits unit min max m5m44800c-5,-5s m5m44800c-6,-6s min max m5m44800c-7,-7s min max delay time, ras low to cas low delay time, ras high to cas low column address hold time after cas low delay time, data to cas low delay time, data to oe low read and refresh cycles note 21: either t rch or t rrh must be satisfied for a read cycle. read cycle time cas low pulse width 0 cas hold time after ras low (note 21) ras low pulse width read hold time after cas high read setup time before cas low (note 21) 0 read hold time after ras high ras hold time after cas low ras hold time after oe low 10000 10000 10000 10000 90 50 13 50 13 0 25 13 0 0 110 60 15 60 15 0 30 15 column address to ras hold time 13 15 ns ns ns ns ns ns ns ns ns ns ns 10000 10000 0 0 130 70 20 70 20 0 35 20 20 cas hold time after oe low t rc t ras t cas t csh t rsh t rcs t rch t rrh t ral t orh t och parameter symbol limits unit min max m5m44800c-5,-5s m5m44800c-6,-6s min max m5m44800c-7,-7s min max 128 ms 16.4 128 16.4 128 (note 18) refresh cycle time * t ref
fast page mode 4194304-bit (524288-word by 8-bit) dynamic ram m5m44800cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44800cj,tp-5,-5s:under development 6 write cycle (early write and delayed write) write cycle time 8 (note 23) ras low pulse width write hold time after cas low write setup time before cas low 0 cas hold time after ras low ras hold time after cas low 10000 10000 10000 10000 90 50 13 50 13 13 13 8 0 10 0 110 60 15 60 15 15 15 10 0 13 15 write pulse width data setup time before cas low or w low data hold time after cas low or w low cas hold time after w low ras hold time after w low ns ns ns ns ns ns ns ns ns ns ns 10000 10000 15 0 130 70 20 70 20 20 20 15 0 20 ns t wc t ras t cas t csh t rsh t wcs t wch t cwl t rwl t wp t ds t dh parameter symbol limits unit min max m5m44800c-5,-5s m5m44800c-6,-6s min max m5m44800c-7,-7s min max read-write and read-modify-write cycles 13 15 20 read write/read modify write cycle time ras low pulse width cas low pulse width cas hold time after ras low read setup time before cas low (note 22) (note 23) 55 55 0 35 80 50 49 126 49 86 0 31 68 43 delay time, cas low to w low delay time, ras low to w low delay time, address to w low ras hold time after cas low (note 23) (note 23) 10000 10000 10000 10000 86 150 100 100 70 70 0 45 95 60 10000 10000 180 120 120 t rwc t ras t cas t csh t rsh t rcs t cwd t rwd t awd oe hold time after w low t oeh ns ns ns ns ns ns ns ns ns ns parameter symbol limits unit min max m5m44800c-5,-5s m5m44800c-6,-6s min max m5m44800c-7,-7s min max note 22: t rwc is specified as t rwc(min) = t rac(max) + t odd(min) + t rwl(min) + t rp(min) +4 t t . note 23: t wcs , t cwd , t rwd and t awd and, t cpwd are specified as reference points only. if t wcs 3 t wcs(min) the cycle is an early write cycle and the dq pins will remain high impedance throughout the entire cycle. if t cwd 3 t cwd(min) , t rwd 3 t rwd(min) , t awd 3 t awd(min) and t cpwd 3 t cpwd(min) (for fast page mode cycle only), the cycle is a read-modify-write cycle and the dq will contain the data read from the selected address. if neither of the above condition (delayed write) of the dq (at access time and until cas or oe goes back to v ih ) is indeterminate. t oeh oe hold time after w low 8 10 15 ns data hold time after cas low or w low t dh data setup time before cas low or w low t ds 0 0 0 ns 10 8 15 ns t wp 10 8 15 ns write pulse width 13 15 20 ras hold time after w low t rwl ns 13 15 20 cas hold time after w low t cwl ns cas low pulse width
fast page mode 4194304-bit (524288-word by 8-bit) dynamic ram m5m44800cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44800cj,tp-5,-5s:under development 7 fast page mode cycle (read, early write, read-write, read-modify-write cycle) (note 24) note 24: all previously specified timing requirements and switching characteristics are applicable to their respective fast page mode cycle. note 25: t ras(min) is specified as two cycles of cas input are performed. note 26: t cp(max ) is specified as a reference point only. fast page mode read/write cycle time (note 25) (note 26) ras low pulse width for read or write cycle cas high pulse width ras hold time after cas precharge delay time, cas precharge to w low (note 23) fast page mode read write/read modify write cycle time 30 35 85 8 48 100000 35 40 100 10 55 100000 12 15 71 80 40 45 115 10 65 100000 15 95 t pc t prwc t ras t cp t cprh t cpwd parameter symbol limits unit min max m5m44800c-5,-5s m5m44800c-6,-6s min max m5m44800c-7,-7s min max ns ns ns ns ns ns cas before ras refresh cycle, extended refresh cycle * (note 27) cas setup time before ras low cas hold time after ras low 5 10 5 10 5 15 t csr t chr t cas cas low pulse width 20 20 25 parameter symbol limits unit min max m5m44800c-5,-5s m5m44800c-6,-6s min max m5m44800c-7,-7s min max ns ns ns note 27: eight or more cas before ras cycles instead of eight ras cycles are necessary for proper operation of cas before ras refresh mode. self refresh cycle * (note 28) t rass cbr self refresh ras low pulse width t rps cbr self refresh ras high precharge time 100 90 100 110 100 130 parameter symbol limits unit min max m5m44800c-5,-5s m5m44800c-6,-6s min max m5m44800c-7,-7s min max ? ns t chs cbr self refresh cas hold time -50 -50 -50 ns
fast page mode 4194304-bit (524288-word by 8-bit) dynamic ram m5m44800cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44800cj,tp-5,-5s:under development 8 timing diagrams (note 29) read cycle t crp t asr t rah t rad t rcd t csh t asc t cah t rcs t ras t rc t rsh t cas t ral t cac t aa t clz t rac t off t rch t rrh t asr t rp hi-z hi-z row column address row address data valid note 29 indicates the don't care input. v ih(min) v in v ih(max) or v il(min ) v in v il(max) indicates the invalid output. address t dzc hi-z t oez t odd t oea t och t dzo t cdd t orh t crp cas w dq 1 ~dq 8 (inputs) ras v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol dq 1 ~dq 8 (outputs) oe v ih v il a 0 ~a 9
fast page mode 4194304-bit (524288-word by 8-bit) dynamic ram m5m44800cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44800cj,tp-5,-5s:under development write cycle (early write) t crp t asr t rah t rcd t csh t asc t cah t wcs t ras t wc t rsh t cas t wch t asr t crp t rp hi-z row column row address data valid address address t ds t dh 9 cas w dq 1 ~dq 8 (inputs) ras v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol dq 1 ~dq 8 (outputs) oe v ih v il a 0 ~a 9
fast page mode 4194304-bit (524288-word by 8-bit) dynamic ram m5m44800cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44800cj,tp-5,-5s:under development write cycle (delayed write) t crp t asr t rah t rcd t csh t asc t cah t rcs t ras t wc t rsh t cas t asr t crp t rp hi-z row column row address data valid address address t clz t wch t cwl t rwl t dh t ds hi-z hi-z t wp t dzo t oez t dzo t odd t oeh 10 cas w dq 1 ~dq 8 (inputs) ras v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol dq 1 ~dq 8 (outputs) oe v ih v il a 0 ~a 9
fast page mode 4194304-bit (524288-word by 8-bit) dynamic ram m5m44800cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44800cj,tp-5,-5s:under development read-write, read-modify-write cycle t crp t asr t rah t rcd t csh t asc t cah t rcs t ras t rwc t rsh t cas t asr t crp t rp hi-z row column row address data valid address address t clz t cwl t rwl t dh t ds hi-z hi-z t wp t dzc t oez t dzo t odd t oeh t awd t cwd t rwd data valid t aa t cac t rac t oea t rad 11 cas w dq 1 ~dq 8 (inputs) ras v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol dq 1 ~dq 8 (outputs) oe v ih v il a 0 ~a 9
fast page mode 4194304-bit (524288-word by 8-bit) dynamic ram m5m44800cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44800cj,tp-5,-5s:under development ras-only refresh cycle t crp t asr t rah t ras t rc t asr t crp t rpc t rp row row address address hi-z 12 cas w dq 1 ~dq 8 (inputs) ras v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol dq 1 ~dq 8 (outputs) oe v ih v il a 0 ~a 9
fast page mode 4194304-bit (524288-word by 8-bit) dynamic ram m5m44800cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44800cj,tp-5,-5s:under development cas before ras refresh cycle, extended refresh cycle * t ras t rc t asr t crp t rpc t rp row column address address t rpc t rc t ras t csr t chr t csr t rpc t cpn t rch t rcs t off hi-z t oez t rp t chr t cdd t odd hi-z 13 cas w dq 1 ~dq 8 (inputs) ras v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol dq 1 ~dq 8 (outputs) oe v ih v il a 0 ~a 9
fast page mode 4194304-bit (524288-word by 8-bit) dynamic ram m5m44800cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44800cj,tp-5,-5s:under development 14 note 30: early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. timing requirements and output state are the same as that of each cycle described above. t crp t asr t rah t rad t rcd t cah t rcs t ras t rc t chr t cac t aa t clz t rac t off t rrh t asr t rp hi-z column row address data valid t ras t rc t rp t rsh row address t asc address t ral hi-z t dzc t cdd hi-z t dzo t oea t orh t odd t oez cas w dq 1 ~dq 8 (inputs) ras v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol dq 1 ~dq 8 (outputs) oe v ih v il a 0 ~a 9 hidden refresh cycle (read) (note 30)
fast page mode 4194304-bit (524288-word by 8-bit) dynamic ram m5m44800cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44800cj,tp-5,-5s:under development fast page mode read cycle t crp t asr t rah t rad t rcd t cah t ras t cp t cac t aa t clz t rac t off hi-z address column row address t asr t rp t cas row hi-z t dzc t dzo t oea t och data valid-1 t csh t pc t cas t cp tcas t rsh column column t cah t asc t cah t asc t rch t rcs t rch t ral t rch t dzc t cdd hi-z t off t aa data valid-2 t clz t cac data valid-3 t aa t clz t cac t off t cpa t oez t och t oea t cpa t oea t oez t odd t och t orh t dzo t odd t oez t dzo t odd address1 address2 address3 t dzc t rcs t cprh hi-z hi-z hi-z 15 t rrh t rcs t asc cas w dq 1 ~dq 8 (inputs) ras v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol dq 1 ~dq 8 (outputs) oe v ih v il a 0 ~a 9
fast page mode 4194304-bit (524288-word by 8-bit) dynamic ram m5m44800cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44800cj,tp-5,-5s:under development fast page mode write cycle (early write) t crp t asr t rah t rcd t cah t wcs t ras t cp t asr hi-z t rp t cas t asc t csh t pc t cas t cp t cas address column row address row column address2 column t cah t asc t cah t asc t wch t rsh t wch t wcs t wcs t wch data valid-1 data valid-2 data valid-3 t ds t dh t ds t dh t ds t dh address1 address3 16 cas w dq 1 ~dq 8 (inputs) ras v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol dq 1 ~dq 8 (outputs) oe v ih v il a 0 ~a 9
fast page mode 4194304-bit (524288-word by 8-bit) dynamic ram m5m44800cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44800cj,tp-5,-5s:under development fast-page mode write cycle (delayed write) t crp t asr t rah t rcd t cah t ras t cp t asr hi-z t rp t cas t asc t csh t pc t cas t rsh address column row address row t cah t asc t rcs t wch data valid-1 t dzc t ds column t rwl t cwl t wp t rcs t wp t cwl hi-z hi-z t dh t ds t dzc t wch data valid-2 t dh hi-z hi-z t clz t clz t dzo t oez t odd t dzo t oez t odd t oeh address1 address2 17 cas w dq 1 ~dq 8 (inputs) ras v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol dq 1 ~dq 8 (outputs) oe v ih v il a 0 ~a 9
fast page mode 4194304-bit (524288-word by 8-bit) dynamic ram m5m44800cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44800cj,tp-5,-5s:under development fast page mode read-write, read-modify-write cycle t crp t asr t rah t rcd t cah t ras t cp t asr hi-z t rp t cas t asc t csh t prwc t cas t rwl address column row address row t cah t asc t rcs t rwd data valid-1 t dzc t ds t cwl t wp t rcs t wp t cwl hi-z hi-z t dh t ds t dzc t cpwd data valid-2 t dh hi-z hi-z t clz t dzo t oez t odd t dzo t oez t oeh t rad t cwd t awd t awd t cwd t aa t cac data valid-1 t aa t cac data valid-2 t clz t rac t oea t cpa t oea t odd address1 18 t wch t wch column address2 cas w dq 1 ~dq 8 (inputs) ras v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol dq 1 ~dq 8 (outputs) oe v ih v il a 0 ~a 9
fast page mode 4194304-bit (524288-word by 8-bit) dynamic ram m5m44800cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44800cj,tp-5,-5s:under development self refresh cycle * (note 28) t rpc t rps t asr t crp row column address address t rass t csr t cpn t rch t rcs t off hi-z t oez t rp t chs t rpc hi-z t cdd t odd 19 cas w dq 1 ~dq 8 (inputs) ras v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol dq 1 ~dq 8 (outputs) oe v ih v il a 0 ~a 9
fast page mode 4194304-bit (524288-word by 8-bit) dynamic ram m5m44800cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44800cj,tp-5,-5s:under development definition of ras only distributed refresh note 28:self refresh sequence two refreshing methods should be used properly depending on the low pulse width(t rass ) of ras signal during self refresh period. 1. distributed refresh during read/write operation (a) timing diagram read/write cycle self refresh cycle read/write cycle t nsd t rass 3 100? t snd last refresh cycle first refresh cycle definition of cbr distributed refresh (including extended refresh) switching from read/write operation to self refresh operation. the time interval t nsd from the falling edge of ras signal in the last ras only refresh cycle during read/write operation period to the falling edge of ras signal at the start of self refresh operation should be set within 16?. switching from self refresh operation to read/write operation. the time interval t snd from the rising edge of ras signal at the end of self refresh operation to the falling edge of ras signal in the first cbr refresh cycle during read/write operation period should be set within 16?. ras (b) definition of distributed refresh ras t ref t ref /1024 refresh cycle read/write cycles t ref / 1024 read/write cycles refresh cycle refresh cycle 20 note: hidden refresh may be used instead of cbr refresh. ras/cas refresh may be used instead of ras only refresh. switching from read/write operation to self refresh operation. the time interval from the falling edge of ras signal in the last cbr refresh cycle during read/write operation period to the falling edge of ras signal at the start of self refresh operation should be set within t nsd (shown in table 2). 1.1 cbr distributed refresh 1.2 ras only distributed refresh the cbr distributed refresh performs more than 1024 constant period (125? max.) cbr cycles within 128ms. all combinations of nine row address signals (a 0 ~a 9 ) are selected during 1024 constant period (16? max.) ras only refresh cycles within 16.4ms. switching from self refresh operation to read/write operation. the time interval from the rising edge of ras signal at the end of self refresh operation to the falling edge of ras signal in the first cbr refresh cycle during read/write operation period should be set within t snd (shown in table 2) read/write cycle cbr distributed refresh ras only distributed refresh read/write self refresh self refresh read/write t nsd 16? t snd 16? t nsd 125? t snd 125? table 2
fast page mode 4194304-bit (524288-word by 8-bit) dynamic ram m5m44800cj,tp-5,-6,-7,-5s,-6s,-7s mitsubishi lsis m5m44800cj,tp-5,-5s:under development definition of cbr burst refresh the cbr burst refresh performs more than 1024 continuous cbr cycles within 16.4ms. definition of ras only burst refresh all combination of nine row address signals (a 0 ~a 9 ) are selected during 1024 continuous ras only refresh cycles within 16.4ms. 2.1 cbr burst refresh 2. burst refresh during read/write operation (a) timing diagram read/write self refresh read/write t nsb t rass 3 100? t snb last refresh cycles first refresh cycles switching from read/write operation to self refresh operation. the time interval t nsb from the falling edge of ras signal in the first cbr refresh cycle during read/write operation period to the falling edge of ras signal at the start of self refresh operation should be set within 16.4ms. switching from self refresh operation to read/write operation. the time interval t snb from the rising edge of ras signal at the end of self refresh operation to the falling edge of ras signal in the last cbr refresh cycle during read/write operation period should be set within 16.4ms. switching from read/write operation to self refresh operation. the time interval from the falling edge of ras signal in the first ras only refresh cycle during read/write operation period to the falling edge of ras signal at the start of self refresh operation should be set within t nsb (shown in table 3). switching from self refresh operation to read / write operation. the time interval from the rising edge of ras signal at the end of self refresh operation to the falling edge of ras signal in the last ras only refresh cycle during read/write operation period should be set within t snb (shown in table 3). ras refresh cycles 1023 cycles refresh cycles 1023 cycles (b) definition of burst refresh 16.4ms read/write cycles ras refresh cycles 1024 cycles 2.2 ras only burst refresh 21 table 3 read/write cycle cbr burst refresh ras only burst refresh read/write self refresh self refresh read/write t nsb +t snb 16.4ms t snb 16.4ms t nsb 16.4ms

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